1. The Field of the Art
The present invention relates to a semiconductor memory device, and more particularly to a row redundancy circuit for repairing row defects generated in a given memory cell by the use of a redundant memory cell.
2. Background of the Related Art
As is well known in the art, a semiconductor memory device has a plurality of memory cells arranged in a matrix of columns and rows. As the capacity of a memory is increased, the semiconductor memory device contains more memory cells. In semiconductor memory devices, if defects are generated in any one memory cell, the semiconductor memory device cannot be used. In order to improve yields even if there is a defective memory cell, methods for replacing the defective normal memory cell with a redundant memory cell are well known.
One example of such a redundancy technique connects a fuse with each bit line or word line of the semiconductor memory device. If defects are generated in a normal memory cell, the fuse connected to the bit line or word line to which the normal memory cell is coupled is cut by a laser beam, for example.
However, as the integration density of semiconductor memory devices increases, it is wasteful of overall chip area to connect a fuse with each bit line and word line of the chip.
Therefore, another method for using redundant memory cells when there is defective normal memory cell provides a redundant row decoder programmed with an address corresponding to the normal row address containing the defective memory cell. This method is the generally preferred method.
Referring to FIG. 1, a conventional row redundancy circuit using redundant row address decoding method is shown. There are provided a first normal memory cell array 20L, a first redundant memory cell array 30L and a second normal memory cell array 20R, a second redundant memory cell array 30R disposed around an input/output (I/O) line 50. Each memory cell group including the redundant and normal memory cell arrays has first and second sense amplifiers 40L, 40R and first and second bit line equalizing circuits 10L, 10R. Moreover, each memory cell group contains first and second sense amplifier control circuits 60L', 60R', first and second redundant word line drivers 70L', 70R', first and second redundant row address decoders or fuse boxes 80L', 80R', and first and second normal word line drivers 90L', 90R'.
FIG. 1 shows a two memory arrays and a plurality of such memory arrays are included in one chip.
In the decoding method of FIG. 1, the redundant memory cell arrays 30L and 30R are respectively selected when a redundant row address is decoded by the redundant row address decoders 80L'and 80R'. The outputs of the redundant memory cell arrays 30L and 30R are enabled by the redundant word line drivers 70L' and 70R'. That is, if defects are generated in the first normal memory cell array 20L, the first redundant memory cell array 30L is used, and if the defects are generated in the second normal memory cell array 20R, the second redundant memory cell array 30R is used. For example, if there are defects in the word line of the first normal memory cell array 20L, an address of the defective word line is programmed in the first fuse box 80L' and the redundant word line corresponding to the defective normal word line is enabled in the redundant memory cell array 30L through the redundant word line driver 70L'. Further, the first sense amplifier 40L is enabled through the first sense amplifier control signal 60L' by the output signal REDL' from the first redundant row address decoder 80L', and as a result, the redundant word line is selected.
FIG. 2 shows a detailed circuit diagram of the first redundant row address decoder 80L' for programming the address in which the defects are generated. As shown, one redundant row address decoder has a plurality of fuses for receiving row addresses. After redundancy programming and during normal operation, a block selection signal .phi.BLKL is applied to node N1. If the defective address is input, node N1 remains at a logic "high" level, thereby generating a redundant word line signal RWL.
In the circuit constructed in the above described manner, the normal memory cell array 20L or 20R have a large number of memory cells. In order to raise the probability of repairing all defective normal memory cells, at least one more redundant row address decoder is needed. As the number of redundant row address decoders increase, so does the need increase for additional word lines and associated redundant memory cells in the redundant memory cell arrays. Thus, the number of repairable word lines is limited by the number of corresponding redundant word lines within the redundant memory cell array. However, if a defective word line does not exist in the first normal memory cell array 20L, but the number of defective word lines generated in the second normal memory cell array 20R is greater than the number of redundant word lines in the second redundant memory cell array 30R, the resulting semiconductor memory device will be inoperable.